1. Field of the Invention
The present invention relates to a ternary value input circuit for digitally realizing ternary value inputs.
2. Description of the Related Art
Ternary value input circuits are known for communicating input terminal states of high level, low level, and open as a level of an output terminal level.
For example, a ternary value input circuit disclosed in FIG. 11 is composed of a voltage divider circuit formed from resistors 10 and 12 connected to an input terminal IN and two inverter circuits 14 and 16 having different threshold voltages.
The first inverter circuit 14 is formed from a P-channel field-effect transistor 14a and an N-channel field-effect transistor 14b and the second inverter circuit 16 is formed from a P-channel field-effect transistor 16a and an N-channel field-effect transistor 16b. The inverter circuit 14 is connected between the input terminal IN and an output terminal OUT1. The inverter circuit 16 is connected between the input terminal IN and an output terminal OUT2.
A ternary value input circuit of the related art analogically detects the state of the input terminal IN in accordance with the transistor threshold voltages and varies the output states of the output terminals OUT1 and OUT2. This resulted in a problem of increased device area due to setting a desired threshold voltage at each transistor.
Furthermore, since it is necessary to complementarily connect each transistor, a problem also results where the operation of the ternary value input circuit becomes unstable when the threshold voltage fluctuates. In addition, there is also a problem of a complex design since it is necessary to take into consideration the fluctuation of the threshold voltage of each transistor.